Path: utzoo!attcan!uunet!jarthur!usc!zaphod.mps.ohio-state.edu!sol.ctr.columbia.edu!cica!iuvax!rutgers!cbmvax!daveh
From: daveh@cbmvax.commodore.com (Dave Haynie)
Newsgroups: comp.sys.amiga.tech
Subject: Re: 2630 Data Cache
Message-ID: <10208@cbmvax.commodore.com>
Date: 16 Mar 90 15:01:43 GMT
References: <345@hawk.isc-br.com> <10121@cbmvax.commodore.com> <10158@cbmvax.commodore.com>
Reply-To: daveh@cbmvax (Dave Haynie)
Organization: Commodore, West Chester, PA
Lines: 51

In article <10158@cbmvax.commodore.com> steveb@cbmvax (Steve Beats) writes:
>In article <10121@cbmvax.commodore.com> daveh@cbmvax (Dave Haynie) writes:
>>Flushing of the cache to support DMA belongs in the device driver.  If
>>that's what's tripping up Blink, its not a Blink problem.  Under 1.3,
>>there's no standard way of doing cache flush, so most device drivers
>>(including those from Commodore) don't do this.

>Ahem, actually Dave, the A2091 does flush the data and instruction caches
>if an 030 is present in the system.  

Cool!  I remember the night you hacked that in there (write allocate bit and
all), but I didn't know if that actually made it to production ROMs or not.
That's the best thing anyone could have done under 1.3 to support data
caching, but won't help on a machine with external cache or a 68040.

>It`s a bit drastic but there is no system supported way of finding out 
>exactly what memory areas are cached, so the whole lot has to go.  I don`t 
>think there`s any way of determining what`s been cached, even in hardware, 
>is there ?

Not from your point of view.  Caches always know what they have cached, but
don't always let you know.  You wouldn't really want to know, anyway.  You
only know what you've modified, so the best thing the OS could do would be
to let you say something like:

	ClearCache(buffer,length);

Or in your language,

	move.l	buffer,d0
	move.l	length,a0
	CALLSYS	ClearCache

Anyway, some cache configurations allow line or block flushes.  Others may
actually snoop the bus in hardware in one of several ways and make the
flush unecessary.  You shouldn't ever have to worry about the implementation
details of the cache consistency mechanism.  I guess the only other extra 
information a cache manager would find useful at some point would be a tag
passed to the the ClearCache() call that indicates where the DMA device was.
It's not always certain that CPU bus DMA vs. expansion bus DMA will have
the same effect on the host CPU's cache.

Anyway, thanks for the news on the 2091 driver.  I've been running with data
cache on.

>	Steve

-- 
Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
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                    Too much of everything is just enough