Path: utzoo!attcan!uunet!cs.utexas.edu!news-server.csri.toronto.edu!utgpu!watserv1!ssingh
From: ssingh@watserv1.waterloo.edu ($anjay "lock-on" $ingh - Indy Studies)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Why The Move To RISC Architectures?  ('386 vs. RISC)
Message-ID: <1558@watserv1.waterloo.edu>
Date: 21 Mar 90 19:28:53 GMT
References: <28011@cup.portal.com> <1990Mar20.233504.4946@seri.gov>
Organization: University of Waterloo
Lines: 49

In article <1990Mar20.233504.4946@seri.gov> marshall@wind55.seri.gov (Marshall L. Buhl) writes:
>
>Just a wild guess.  Hardware guys like RISC, software guys like CISC.
>RISC puts the work on the shoulders of the software folks.  It's easier
>to impliment RISC in hardware. 

My question isn't exactly germaine to the newsgroup, but I'll ask in the
hope that because of the high volume here, someone might be able to
answer this for me.

Daniel Hillis, chief designer of the Connection Machine said in
his 1985 thesis on the architecture of this machine that the only
way to achieve continued increases in computer power is to abandon
the current design philosophy in hardware engineering pioneered by
Von Neumann. Since today's computers are essentially implementations
of a Turing machine they are extremely flexible when it comes to
applications programming. That is, given liberal time and memory 
constraints, ANYTHING can be simulated (the Church-Turing thesis).

Now what happens is that everything is encoded in memory and
must then travel to the processor through a bus (with a limited
bandwidth) for processing, and then it must be re-written. This
limiting bandwidth was not a problem until people like AI researchers
and fluid dynamics people began developing extremely powerful 
algorithms that often are very iterative. Also, microprocessor
development has been accelerating, while memory is not able 
to keep up anymore.

Anyone who has a computer with "memory wait-states" will attest
to this. So the solution Hillis argues, is to break up this
Von Neumann bottleneck over thousands (65536 of them) of processors
and do computations in parallel. Each processor can communicate
with any other by message passing, and each has it's own
local memory.

Such computers lend themselves well to applications which can
breakdown naturally into chunks which can be executed in parallel.
Thinking appears to be one of these, hence the current interest
in neural-net models.

Having said all this, my question: What type of processor lends
itself better to highly parallel architectures, RISC or CISC?


-- 
"No one had the guts... until now..."  
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