Path: utzoo!attcan!uunet!cs.utexas.edu!tut.cis.ohio-state.edu!ucsd!ames!pasteur!agate!shelby!portia!dhinds
From: dhinds@portia.Stanford.EDU (David Hinds)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Mixing DRAM speeds
Message-ID: <10408@portia.Stanford.EDU>
Date: 21 Mar 90 19:34:35 GMT
References: <2340003@hpldsla.HP.COM>
Sender: David Hinds <dhinds@portia.stanford.edu>
Organization: Stanford University
Lines: 23

In article <2340003@hpldsla.HP.COM>, djw@hpldsla.HP.COM writes:
> A friend of mine just added a 2 meg bank of 1megx1bit  80ns DRAM
> to his 80286, NEAT chip set clone.  The  computer  already had a
> 1/2 meg bank of 256kx1bit 120ns DRAM.
> 
> He configured the memory controller (is that right??) for 120ns
> memory.
> 
> So, all  should  work  fine, and he should  get 2.5 megs  with a
> speed of 120ns - right?
> 
    The problem may be that the chip set cannot handle mixing two
bank sizes.  My chip set is different, but I know that it will only
allow either all 256K-wide or all 1M-wide memory modules.
    In general, I think DRAM's with different speeds are like CPU's
with different speeds - a faster DRAM simply passed a more stringent
quality control test.  I think this applies to 80ns vs 120ns chips,
**where the chip design is the same**.  However, 256K chips may have
different refresh requirements from 1M chips, even at the SAME speed.
I don't know whether this is true or not.

 -David Hinds
  dhinds@popserver.stanford.edu