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From: nelson_p@apollo.HP.COM (Peter Nelson)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Why The Move To RISC Architectures?
Message-ID: <49546677.20b6d@apollo.HP.COM>
Date: 21 Mar 90 17:24:00 GMT
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Organization: Hewlett-Packard Apollo Division - Chelmsford, MA
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 :> Also, since the 80386 has a more complex instruction set and does
 :> more work in a given instruction than does a typical RISC chip,
 :> does comparing MIPS figures between RISC and non-RISC
 :> architectures really tell you anything of worth?


 Obviously the instruction sets of different machines are very different.
 This isn't just a problem between RISC and CISC but between different CISC
 machines too.   The venerable Z80's instruction set was 4 ticks for r-r ops,
 7 ticks for 8 bit r-m ops, 10 ticks for 16 bit r-m ops, etc.  You could
 easily make a case for an "average" program's mix to be ~8 ticks per instruction
 since the 4 and 7 tick instructions predominate and drag the average down.
 Does this mean that a 4 MHz Z80 was a full half MIPS???   Of course not.

 NOBODY I know is compring "RISC MIPS" to "CISC MIPS".  The
 standard use of the term "MIPS" these days is  1 VAX-11/780 MIPS.

 Obviously you are still at the mercy of the compiler for such comparisons 
 although this is not such a bad thing since you would also be at the
 compiler's mercy in the real world of software development.   In other
 words its perfectly reasonable to say "using the best compiler we could
 find, machine X is 2X as fast as machine Y using the best compiler we could
 find for machine Y.   

                                                       ---Peter