Path: utzoo!utgpu!news-server.csri.toronto.edu!helios.physics.utoronto.ca!ists!yunexus!maccs!cs4g6ag
From: cs4g6ag@maccs.dcss.mcmaster.ca (Stephen M. Dunn)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Why The Move To RISC Architectures?  ('386 vs. RISC)
Message-ID: <260970FD.20500@maccs.dcss.mcmaster.ca>
Date: 23 Mar 90 00:42:37 GMT
References: <28011@cup.portal.com> <1990Mar20.233504.4946@seri.gov> <628@s3.ireq.hydro.qc.ca>
Reply-To: cs4g6ag@maccs.dcss.mcmaster.ca (Stephen M. Dunn)
Organization: McMaster University, Hamilton, Ontario
Lines: 17

In article <628@s3.ireq.hydro.qc.ca> robert@ireq.hydro.qc.ca (R.Meunier 8516) writes:
$	Once a compiler is completed for a RISC Architecture, it should
$be easely ported to another one because the RISC instruction between
$two RISC microprossesor should be the almost the same.

   Not really.  Different RISC designs use different register schemes,
have different pipelines, etc.  An extreme example would be porting from
some RISC design to a MIPS processor, where the compiler has to ensure that
the instructions it generates will not clash as they go through the
CPU's pipeline (this is implemented in hardware on most other designs).
Also, the optimizer requires a lot of changes since different optimization
strategies provide different performance on different RISC architectures.
-- 
Stephen M. Dunn                               cs4g6ag@maccs.dcss.mcmaster.ca
          <std_disclaimer.h> = "\nI'm only an undergraduate!!!\n";
****************************************************************************
    "So sorry, I never meant to break your heart ... but you broke mine."