Path: utzoo!attcan!uunet!mcsun!ukc!edcastle!aikc
From: aikc@castle.ed.ac.uk (Kenneth Cameron)
Newsgroups: comp.sys.m68k
Subject: Re: RAM info wanted
Message-ID: <2901@castle.ed.ac.uk>
Date: 17 Mar 90 17:00:05 GMT
References: <2240002@hpsad.HP.COM>
Reply-To: aikc@castle.ed.ac.uk (Kenneth Cameron)
Organization: Edinburgh University Computing Service
Lines: 23


I spent several weeks trying to track down this type of information.
As you say, most tend to just be block diagrams showing none of the
details. I finally got hold of a book, which not only gave an example
circuit for dynamic refresh control (using 74xx chips), but explained all
the timing that must be considered. It's called

	Microprocessor Systems Design
	68000 Hardware, Software, and Interfacing.

	By Alan Clements (Published by PWS-KENT)
	ISBN 0-87150-095-7

The example design is taken from Motorola ECB. It has a seven bit refresh
clock, but more stages could be added,(Thats what I intend to do).
It also covers address multiplexing etc. The book also covers details of
other 68000 systems design.


-- 
,Kenneth.
K.Cameron@uk.ac.edinburgh                                kenneth@uk.ac.cs.tardis
            "I'll think of something funny sometime, I promise."