Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!wuarchive!usc!snorkelwacker!apple!archer!dwb
From: dwb@archer.apple.com (David W. Berry)
Newsgroups: comp.sys.mac.hardware
Subject: Re: Apple Announces High Performance Products
Message-ID: <7307@goofy.Apple.COM>
Date: 21 Mar 90 01:47:55 GMT
References: <39637@apple.Apple.COM> <1990Mar20.161729.9549@chaos.cs.brandeis.edu>
Sender: usenet@Apple.COM
Organization: Apple Computer
Lines: 15

In article <1990Mar20.161729.9549@chaos.cs.brandeis.edu> topgun@chaos.cs.brandeis.edu (Chandra Bajpai) writes:
>Can anybody elaborate on the latched write design and I/O processors
>(design and how it actually speeds up the system)?
	I probably misunderstand, but my understanding is that the
"latched write" design allows the cache to overlap reads and writes
to memory and utilizes some patented processes to implement.
	There are to IOP's, each is a modified 6502, including 32K of
memory.  One is attached to the serial chip and the other to ADB and
who knows what-all-else.  The serial chip does things like runs the
AppleTalk protocols, deals with interrupts, etc. and allows the 030
to deal with things on a strictly packet basis.  The other one among
other things deals with the periodic polling required of ADB.
	
	David W. Berry			A/UX Toolbox Engineer
	dwb@apple.com