Xref: utzoo comp.lang.c:27146 comp.lang.misc:4611 comp.arch:14790 Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!iuvax!rutgers!texbell!sugar!ficc!peter From: peter@ficc.uu.net (Peter da Silva) Newsgroups: comp.lang.c,comp.lang.misc,comp.arch Subject: Re: function calls Message-ID: <54F26+5ggpc2@ficc.uu.net> Date: 23 Mar 90 03:02:47 GMT References: <29585@amdcad.AMD.COM> <14285@lambda.UUCP> Reply-To: peter@ficc.uu.net (Peter da Silva) Followup-To: comp.lang.misc,comp.arch Organization: Xenix Support, FICC Lines: 16 (for comp.arch folks, Jim is basically saying that the more registers you have, the better, because it lets you put more variables in registers) But, Jim, registers aren't free. The more registers you have the more bits you have to hide in your carefully crafted instruction set to specify registers. Modern RISC processors have up to 4 arguments to a given instruction, so even if they're all registers (no mixed-mode instructions) and you only have 16 registers, that's 16 bits gone right there. Now, let's add some more bits to specify constants and maybe some addressing modes, and you can run out of bits pretty quickly. With 64 registers (about the most I'd expect you to be happy with), and immediate operands that would leave you with about 5 bits to specify the instruction. Now suppose you have room on the chip for 512 registers... why *not* use register windows, or a stack cache, or something similar instead of just making the instruction wider? -- _--_|\ `-_-' Peter da Silva. +1 713 274 5180. . / \ 'U` \_.--._/ v