Path: utzoo!attcan!uunet!cs.utexas.edu!wuarchive!kuhub.cc.ukans.edu!markv
From: markv@kuhub.cc.ukans.edu
Newsgroups: comp.sys.amiga.tech
Subject: Re: 2630 Data Cache
Message-ID: <22630.2610a837@kuhub.cc.ukans.edu>
Date: 28 Mar 90 18:04:07 GMT
References: <345@hawk.isc-br.com> <10121@cbmvax.commodore.com> <10158@cbmvax.commodore.com> <10208@cbmvax.commodore.com>
Organization: University of Kansas Academic Computing Services
Lines: 27

> That's the best thing anyone could have done under 1.3 to support data
> caching, but won't help on a machine with external cache or a 68040.

But it wont be a problem on a 68040.
 
> Anyway, some cache configurations allow line or block flushes.  Others may
> actually snoop the bus in hardware in one of several ways and make the
> flush unecessary.

The 68040 does this both ways.  It snoops the bus for accesses to
memory it has cached.  If it is a write access, it turns around and
marks those cache entries invalid, it senses a read access, it
inhibits the read cycle and takes it over, putting out the cached
value for whatever is trying to read it (or flushing the entries).

Of course this only works on machines that fully implement the 68040s
cache and bus control lines.

-- 
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