Path: utzoo!utgpu!news-server.csri.toronto.edu!clyde.concordia.ca!uunet!cs.utexas.edu!tut.cis.ohio-state.edu!pt.cs.cmu.edu!b.gp.cs.cmu.edu!ralf From: ralf@b.gp.cs.cmu.edu (Ralf Brown) Newsgroups: comp.sys.ibm.pc Subject: Re: Why The Move To RISC Architectures? ('386 vs. RISC) Message-ID: <8564@pt.cs.cmu.edu> Date: 23 Mar 90 04:50:27 GMT References: <28011@cup.portal.com> <26083220.22927@maccs.dcss.mcmaster.ca> <10453@portia.Stanford.EDU> Organization: Carnegie-Mellon University, CS/RI Lines: 16 In article <10453@portia.Stanford.EDU> dhinds@portia.Stanford.EDU (David Hinds) writes: }some RISC features. Why? Because it is fast? It seems to me that the }80486 is instead the antithesis - and nemesis - of RISC technology. If }we now have the ability to design a CISC processor so efficiently that }most of its instructions take only a cycle or two, why move to a less }complex architecture? The 80486 had sufficient circuit space left over }for a respectable amount of support stuff, as well. You could say, well, Yeah, but how many RISC CPUs have 1.2 million transistors? That's something like EIGHT to TEN times as many gates as the typical RISC CPU.... -- {backbone}!cs.cmu.edu!ralf ARPA: RALF@CS.CMU.EDU FIDO: Ralf Brown 1:129/46 BITnet: RALF%CS.CMU.EDU@CMUCCVMA AT&Tnet: (412)268-3053 (school) FAX: ask DISCLAIMER? | _How_to_Prove_It_ by Dana Angluin 3. by vigorous handwaving: What's that?| Works well in a classroom or seminar setting.