Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!wuarchive!mit-eddie!uw-beaver!sumax!quick!srg
From: srg@quick.COM (Spencer Garrett)
Newsgroups: comp.sys.m68k
Subject: Re: 68040 Transparent Translation problem
Message-ID: <7814@quick.COM>
Date: 27 Mar 90 09:46:43 GMT
References: <702@ssp11.idca.tds.philips.nl>
Organization: Quicksilver Engineering, Seattle
Lines: 29

In article <702@ssp11.idca.tds.philips.nl>, dolf@idca.tds.PHILIPS.nl (Dolf Grunbauer) writes:
-> 
-> The MC68040 has four independent transparent translation registers. Two
-> for data, two for instructions. Reading the User's Manual I get confused
-> about this `independent' as it states in paragraph 6.3 (page 6-12):
-> 
-> 	Also, since the instruction memory unit is used only for instruction
-> 	prefetches, different instruction and data TT registers can cause PC
-> 	relative operand fetches to be translated differently from instruction
-> 	prefetches.
-> 
-> (so PC relative addressing uses the data TT's, not the instruction TT's).

Data accesses use the data TT's, regardless of addressing mode.

-> What I get from this is that the data TT's must always be the same as the
-> instruction TT's otherwise the code may not run properly. If this is the
-> case then why are there different instruction and data TT's ? Note that the
-> translation table structure of the MC68040 MMU does not distinguish between
-> data and instruction.

There are separate TT's because there are separate MMU's and caches.
The 68040 runs a Harvard architecture internally, so data and instruction
accesses proceed in parallel until they have to use the (single) external
bus. PC relative references work just fine as long as the data addresses
they generate are mapped as part of the data space.  The reason for letting
you write to 4 separate TT's rather than 2 copies of 2 logical TT's is so
that you can control the caching methods independently.  (This is my
speculation, of course.  I can't speak for Motorola.)