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From: caveh@csl.sri.com (Caveh Jalali)
Newsgroups: comp.sys.m68k
Subject: Re: 68040 Transparent Translation problem
Message-ID: <16939@hercules.csl.sri.com>
Date: 28 Mar 90 05:55:36 GMT
References: <702@ssp11.idca.tds.philips.nl>
Sender: usenet@csl.sri.com
Organization: Computer Science Lab, SRI International, Menlo Park, CA
Lines: 54

In article <702@ssp11.idca.tds.philips.nl> dolf@idca.tds.PHILIPS.nl (Dolf Grunbauer) writes:
>
>The MC68040 has four independent transparent translation registers. Two
>for data, two for instructions. Reading the User's Manual I get confused
>about this `independent' as it states in paragraph 6.3 (page 6-12):
>
>	Also, since the instruction memory unit is used only for instruction
>	prefetches, different instruction and data TT registers can cause PC
>	relative operand fetches to be translated differently from instruction
>	prefetches.
>
>(so PC relative addressing uses the data TT's, not the instruction TT's).
>
>What I get from this is that the data TT's must always be the same as the
>instruction TT's otherwise the code may not run properly. If this is the
>case then why are there different instruction and data TT's ? Note that the
>translation table structure of the MC68040 MMU does not distinguish between
>data and instruction.

"it's not a bug, it's a feature!"
the key is that the two MMU's are completely independent.  also, the
translation caches are completely independent.  this means that each
MMU has to be programmed independently -- to make life easy (sane)
you basically configure both MMU's the same way.  in the case of the
TT's you would normally put them at the same virtual address in both
MMU's, but can choose to do it differently for some special effect.
example:  you have EPROM at some address which you run your boot code
from -- program this into your instr-MMU + you have some scratch
ram which you use for stack, etc... this goes into your data-MMU.
there is no need for one MMU to know about the other MMU's TT entires.

the following 2 code segments will give different results IFF the
TT's are configured differently in each MMU.  it's not that the code
won't work, it does exactly what it's spec'd to do.  if the MMU's are
configured the same, we have a special case because both code
segments give the same result.

in case_1 data fetch goes thru the instr-MMU, whereas in case_2
the fetch goes thru the data-MMU.

case_1:
	movl	pc@(data),d0		(FCODE=CODE)
	...
data:
	long	<value>

case_2:
	lea	pc@(data),a0
	movl	a0@,d0			(FCODE=DATA)
--
00c -- Who was that masked interrupt?
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