Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!uunet!decwrl!shelby!awang@isl.Stanford.EDU
From: awang@isl.Stanford.EDU (Avery Wang)
Newsgroups: comp.sys.next
Subject: Re: What NeXT *should* do next.
Message-ID: <35@isl.stanford.edu>
Date: 24 Mar 90 05:51:54 GMT
References: <1378@shelby.Stanford.EDU> <9967@batcomputer.tn.cornell.edu> <424@toaster.SFSU.EDU> <Eqe#zm3@cs.psu.edu>
Sender: awang@isl.Stanford.EDU (Avery Wang)
Reply-To: awang@isl.UUCP (Avery Wang)
Organization: Stanford University
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In article <Eqe#zm3@cs.psu.edu> melling@cs.psu.edu (Michael D Mellinger) writes:

>answer(they're betting their futures on it).  The MIPS R4000 is
>suppose to execute 50mips at 25Mhz.  That's performance!!  And what is
                    ^^^^^^^^^^^^^^^

So that's one instructions per half cycle.  How can this be?  Is the 
MIPS R4000 some sort of multiprocessor?  How does it handle conditional
branching?

-Avery