Path: utzoo!attcan!uunet!tut.cis.ohio-state.edu!ucbvax!A.ISI.EDU!ENGLE
From: ENGLE@A.ISI.EDU
Newsgroups: comp.sys.transputer
Subject: iWarp
Message-ID: <[A.ISI.EDU]28-Mar-90.15:22:58.ENGLE>
Date: 28 Mar 90 20:22:00 GMT
Sender: daemon@ucbvax.BERKELEY.EDU
Organization: The Internet
Lines: 36


Some specs on the iWarp:

- Two modes of communication: message-passing, or systolic.
- Four communications links each capable of 40MBytes/s each.
- On-chip communications agent which supports cut-through and worm-hole 
	routing in hardware.
- 20MFlops floating point performance.
- 20MIPS integer performance.
- Large instruction word format.
- 64-bit memory access.
- On-chip bug/break features.

The communications agent operates in two modes, message-passing or systolic.
In message-passing the system supports hardware routing of multiple logical 
connections per physical connection.  In systolic mode, the processor supports
a dataflow style communications in which the removal of an operand from the 
stream allows the next operand to move up in the stream.  These operands go
directly into the CPU registers where they can become part of a computation
and be placed back into the stream with very little delay.  

The computation agent contains seperate units for integer, floating-point, and
streaming/spooling.  All of these units have access to a 15-port register file
with 128 32-bit locations, accessible as bytes, half-words, or double words.
All of these units can operate independently of other units on the chip.
The register unit is capable of nine read and six write operations in a single
clock period.  The streaming/spooling unit handles the storage of incoming 
data into memory.

This chip is a serious contender against the transputer.  It is currently 
being marketed toward signal processing applications, but its not hard to
see the applications in transputer-like workstations.

Steven W. Engle
Senior AI Software Engineer
MIMD Systems, Inc.