Path: utzoo!attcan!uunet!jarthur!usc!apple!portal!cup.portal.com!mslater
From: mslater@cup.portal.com (Michael Z Slater)
Newsgroups: comp.arch
Subject: Re: "zero wait states"
Message-ID: <28673@cup.portal.com>
Date: 7 Apr 90 04:53:07 GMT
References: <719@optis31.UUCP> <4141@labtam.oz> <6543@dell.dell.com>
  <10828@portia.Stanford.EDU> <6561@dell.dell.com>
Organization: The Portal System (TM)
Lines: 22

>:In article <6543@dell.dell.com>, sauer@dell.dell.com (Charlie Sauer) writes:
>:: 
>:: Which others have you looked at?  I would think they would be older parts
>:: since 386 pipelining is going/has gone away, I believe.
>:
>:    Where did you hear this?  ...
>
>I was misinformed.  My source says there had been a plan to discontinue suppor
t
>of pipelined addressing, but the plan was dropped.

When Intel moved to the 1-micron CHMOS-IV process last spring, they broke
some logic in the 386 that, under certain rare conditions, caused the
prefetch queue to be corrupted when running in pipelined bus mode. The
workaround is simply not to use pipelined mode.  This was deemed to be not
a big problem, since most systems were using cache at the higher clock rates,
and generally not using pipelining, and slow clock rate parts were still 
coming off the 1.5-micron process.  As of last July, Intel expected to ship
D1 parts with this bug fixed by the end of '89; I don't know what actually
happened.

Michael Slater, Microprocessor Report   mslater@cup.portal.com