Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!samsung!dali!uakari.primate.wisc.edu!zaphod.mps.ohio-state.edu!sunybcs!uhura.cc.rochester.edu!rochester!pt.cs.cmu.edu!andrew.cmu.edu!zs01+ From: zs01+@andrew.cmu.edu (Zalman Stern) Newsgroups: comp.arch Subject: Re: Parallel cache and TLB lookup Message-ID: Date: 6 Apr 90 18:46:23 GMT References: <1830@gannet.cl.cam.ac.uk> Organization: Information Technology Center, Carnegie Mellon, Pittsburgh, PA Lines: 22 In-Reply-To: <1830@gannet.cl.cam.ac.uk> [Discussion of address aliasing problems on the IBM Risc System/6000] In the Mach port to the RIOS, we get around this problem by almost always running in virtual mode. The wired kernel memory (text segment and unpageable data mapped at boot time) is mapped virtual=real. The only time the machine goes into real mode is on interrupts. (System calls and traps do not have to go into real mode on this machine.) Memory accessed in an interrupt handler has to be wired anyway (and is usually statically allocated as well). Besides, device drivers already have to deal with some cache flushing since there is no hardware to provide consistency between the cache and IO space. Since the RIOS has an inverted page table, aliases between virtual addresses requires taking page faults to move the correct virtual address into the IPT. (That is is one alias is in the IPT, accessing that memory through a different alias will take a page fault.) When this happens, the fault handler flushes that page from the cache as well. Sincerely, Zalman Stern Internet: zs01+@andrew.cmu.edu Usenet: I'm soooo confused... Information Technology Center, Carnegie Mellon, Pittsburgh, PA 15213-3890