Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!sunybcs!uhura.cc.rochester.edu!rochester!pt.cs.cmu.edu!andrew.cmu.edu!zs01+ From: zs01+@andrew.cmu.edu (Zalman Stern) Newsgroups: comp.arch Subject: Re: Black magic, IBM RIOS. Message-ID: Date: 6 Apr 90 18:57:06 GMT References: , <8728@pt.cs.cmu.edu> Organization: Information Technology Center, Carnegie Mellon, Pittsburgh, PA Lines: 21 In-Reply-To: <8728@pt.cs.cmu.edu> Excerpts from netnews.comp.arch: 4-Apr-90 Re: Black magic, IBM RIOS. Donald Lindsay@MATHOM.GA (1977) > Each cache-load cycles the data bus 8 times, so programs using large > strides would probably want to use uncached loads and stores. A > quick search didn't turn up any mention that the RS allows that. > Does anyone know that for sure? And does anyone have similar numbers > for, say, the i860, which was specifically intended to be used that > way? > -- > Don D.C.Lindsay Carnegie Mellon Computer Science To the best of my knowledge, the only way to do uncached loads on an IBM RISC System/6000 is to map the memory through IO space. This is slow (rumored to be ~20 cycles per access). Sincerely, Zalman Stern Internet: zs01+@andrew.cmu.edu Usenet: I'm soooo confused... Information Technology Center, Carnegie Mellon, Pittsburgh, PA 15213-3890