Path: utzoo!attcan!uunet!fernwood!portal!cup.portal.com!mmm
From: mmm@cup.portal.com (Mark Robert Thorson)
Newsgroups: comp.arch
Subject: Questions about DRAM's
Message-ID: <28686@cup.portal.com>
Date: 7 Apr 90 19:51:53 GMT
Organization: The Portal System (TM)
Lines: 29

Will there ever come a time when more than two portions of the address
are strobed into the multiplexed address pins of DRAM's?  For example,
will there be something like a page address, in addition to row and column?
Does anyone already do this?

Or will it make more sense to multiplex address and data, sending in perhaps
a 32- or 64-bit physical address, then reading data on the same pins?  This
would be the most efficient use of pins if the host processor always bursts
its reads and writes, and the DRAM can send a new consecutive data item
on every clock.

Or will a more clever configuration be used?

Also, will pseudostatic DRAM's eventually win?  I notice the Hitachi PRAM's
are just as dense as their DRAM's (4Mb).  I suppose this means that the extra
logic required to get the maximum user-friendly refresh mechanism is now
a tiny % when compared to the size of the memory planes.

Or, will SRAM's eventually surpass DRAM's in density?  I've heard this 
comparison:  how small can you make a capacitor / how small can you make
six transistors.  Will transistors eventually become so small that six
interconnected transistors together are smaller than a minimum-size
capacitor.  Or will the capacitors scale down as far as transistors
can go?

(Please indicate year if you think one technology will prevail first,
then another will take over.  If two technologies co-exist, I want to know
which one will be used for high-end personal computers.  State whether
you're assuming a "personal computer" is desktop, laptop, brain implant, etc.)