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From: pi@maserati.isi.edu (Jen-I Pi)
Newsgroups: comp.arch
Subject: Re: 16M DRAM
Message-ID: <12796@venera.isi.edu>
Date: 8 Apr 90 01:44:07 GMT
References: <2323@psuhcx.psu.edu>
Sender: news@venera.isi.edu
Reply-To: pi@maserati.isi.edu (Jen-I Pi)
Organization: USC-Information Sciences Institute
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In article <2323@psuhcx.psu.edu>, davidt@psuhcx.psu.edu (Thomas S.
David) writes:
> Hi out there...
> 	I was wondering if anyone out there knew what technology was used 
> in the IBM 16M DRAM which was first announced sometime in FEB 1990. i.e.,
> specifically interested in knowing gate lengths etc., I guess TI announced
> a 16M DRAM too a few days after this. I hope this information is not
> classified, I need the info for a class.
> 	
> 			Thanks in advance,
> 				Tom.

I don't have the exact info about this. But based on the fact that Japanese
is able to fab 4M and 16M DRAM in 0.8um and 0.5um CMOS respectively in
feature size, I would guest IBM's technology should be around 0.5um,
give or take 0.1um.


Jen-I pi@vlsi-cad.isi.edu :-)
MOSIS Project, USC/ISI