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From: raje@dolores.Stanford.EDU (Prasad Raje)
Newsgroups: comp.arch
Subject: Re: 16M DRAM
Message-ID: <RAJE.90Apr8123315@dolores.Stanford.EDU>
Date: 8 Apr 90 19:33:15 GMT
References: <2323@psuhcx.psu.edu>
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Organization: Center for Integrated Systems, Stanford
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In-reply-to: davidt@psuhcx.psu.edu's message of 7 Apr 90 22:32:02 GMT


In article <2323@psuhcx.psu.edu> davidt@psuhcx.psu.edu (Thomas S. David) writes:

	   I was wondering if anyone out there knew what technology was used 
   in the IBM 16M DRAM which was first announced sometime in FEB 1990. i.e.,
   specifically interested in knowing gate lengths etc., I guess TI announced
   a 16M DRAM too a few days after this. I hope this information is not
   classified, I need the info for a class.


You can get detailed info from the ISSCC Technical Digest 1990, pp 232.
Here is some brief information anyway - 

Technology:		0.5um CMOS
cell type:		trench
cell size:		4.13 um^2
die size:		140.9 mm^2
cell capacitance:	100 fF
access time:		50 ns
fast page access:	16 ns
error correction:	single error correct/double error detect
redundancy:		(is present, kinda hard to describe
			without also describing the array layout)
supply voltage:		either 5 or 3V external

I must point out that 16M DRAMS were announced by Mitsubishi, NEC,
and Toshiba at ISSCC 89, one year before IBM.

Prasad