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From: kyriazis@iear.arts.rpi.edu (George Kyriazis)
Newsgroups: comp.arch
Subject: Re: 16M DRAM
Message-ID: <5#P#^P#@rpi.edu>
Date: 9 Apr 90 16:27:45 GMT
References: <2323@psuhcx.psu.edu> <12796@venera.isi.edu>
Organization: Rensselaer Polytechnic Institute, Troy NY
Lines: 25

In article <2323@psuhcx.psu.edu>, davidt@psuhcx.psu.edu (Thomas S.
David) writes:
> Hi out there...
> 	I was wondering if anyone out there knew what technology was used 
> in the IBM 16M DRAM which was first announced sometime in FEB 1990. i.e.,
> specifically interested in knowing gate lengths etc., I guess TI announced
> a 16M DRAM too a few days after this. I hope this information is not
> classified, I need the info for a class.
> 	
> 			Thanks in advance,
> 				Tom.

I know that the IBM design uses trench-type capacitors for thier cells.  This
means that the cell capacitor is extended INTO the silicon to increase 
capacitance per unit area.  The japanese designs, place the capacitor in the
form of a multi-platter hard disk above the cell.

the IBM "trech" design is more difficult to fabricate than the other, but
I guess they succeeded.


----------------------------------------------------------------------
  George Kyriazis                 kyriazis@turing.cs.rpi.edu
				  kyriazis@rdrc.rpi.edu
 				  kyriazis@iear.arts.rpi.edu