Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!mcsun!ukc!dcl-cs!aber-cs!odin!pcg From: pcg@odin.cs.aber.ac.uk (Piercarlo Grandi) Newsgroups: comp.arch Subject: Re: Black magic, IBM RIOS. Message-ID: Date: 9 Apr 90 11:05:04 GMT References: <1990Apr4.140713.8996@specialix.co.uk> Sender: pcg@aber-cs.UUCP Organization: Coleg Prifysgol Cymru Lines: 48 In-reply-to: jpp@specialix.co.uk's message of 4 Apr 90 14:07:13 GMT In article <1990Apr4.140713.8996@specialix.co.uk> jpp@specialix.co.uk (John Pettitt) writes: Path: aber-cs!gdt!dcl-cs!ukc!slxsys!jpp From: jpp@specialix.co.uk (John Pettitt) Newsgroups: comp.arch Date: 4 Apr 90 14:07:13 GMT References: Organization: Specialix International, London Lines: 20 pcg@odin.cs.aber.ac.uk (Piercarlo Grandi) writes: >Executing the two versions, whose inner loop come to be 7 instructions >and 10 instructions, gives me times of 1.3 seconds and 10.4 seconds. >Look again at the figures: > register: 16M*7 instructions in 1.3 s > volatile static: 16M*10 instructions in 10.4 s Same test on a mips 3240 (25Mhz R3000) register: 1.0 s volatile static: 8.9 s This I cannot believe. The numbers above say that a 20Mhz RIOS does in the most favorable conditions 70 integer native MIPS, i.e. around 3 instructions per Hz (BLACK MAGIC!). Your register timings for the 3240 (and the MIPS inner loop is 4 instructions) imply 16M*4 instructions in 1 second, that is 64 MIPS. I cannot believe that the 25 Mhz R3000 os superscalar as well. There is also another reason I cannot believe your 3240 figures; I have tried the same loop on a 16.67 Mhz DECstation and it takes 3.5 seconds, and on a 5840 it takes 2.8 seconds. This is the expected value. I will be shortly posting a full table with several machines and some notes on them. One interesting result I can anticipate is that the IBM machine is the fastest, and it also has the largest multiple between the register vs. the memory based loop. Other machines usually have a factor of 3-5 at most. One of my interests in compiling this table is to see the ration between native MIPS, Mhz, and *transistor counts* (the issue is internal vs. external parallelism). -- Piercarlo "Peter" Grandi | ARPA: pcg%cs.aber.ac.uk@nsfnet-relay.ac.uk Dept of CS, UCW Aberystwyth | UUCP: ...!mcvax!ukc!aber-cs!pcg Penglais, Aberystwyth SY23 3BZ, UK | INET: pcg@cs.aber.ac.uk