Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!execu!sequoia!rpp386!jfh From: jfh@rpp386.cactus.org (John F. Haugh II) Newsgroups: comp.arch Subject: Re: Black magic, IBM RIOS. Message-ID: <18208@rpp386.cactus.org> Date: 10 Apr 90 04:05:51 GMT References: <1990Apr4.140713.8996@specialix.co.uk> Reply-To: jfh@rpp386.cactus.org (John F. Haugh II) Organization: Lone Star Cafe and BBS Service Lines: 18 In article pcg@odin.cs.aber.ac.uk (Piercarlo Grandi) writes: >This I cannot believe. The numbers above say that a 20Mhz RIOS does in >the most favorable conditions 70 integer native MIPS, i.e. around 3 >instructions per Hz (BLACK MAGIC!). Your register timings for the 3240 >(and the MIPS inner loop is 4 instructions) imply 16M*4 instructions in >1 second, that is 64 MIPS. I cannot believe that the 25 Mhz R3000 os >superscalar as well. I tested a 20MHz S/6000 with a backlevel compiler and managed to [ only ] produce 2.1 seconds for the register loop. I don't know if it was 7 instructions, but assuming it was yields 4096 x 4096 x 7 / 2.1 = 55,924,053 instructions per second which translates to 2.8 instructions per cycle. -- John F. Haugh II UUCP: ...!cs.utexas.edu!rpp386!jfh Ma Bell: (512) 832-8832 Domain: jfh@rpp386.cactus.org