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From: rtrauben@cortex.Sun.COM (Richard Trauben)
Newsgroups: comp.arch
Subject: Re: RISC definition (was: Why The Move To RISC) (long)
Message-ID: <151@exodus.Eng.Sun.COM>
Date: 5 Apr 90 15:11:31 GMT
References: <2756@sunquest.UUCP>
Sender: news@exodus.Eng.Sun.COM
Reply-To: rtrauben@cortex.EBay.Sun.COM (Richard Trauben)
Organization: Sun Microsystems, Inc.  Mt. View, Ca.
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> How about a definition of RISC (we can all agree upon):
This reminds me of the meta-religous arguments regarding
how many angels fit on the head of a pin. -:) 
Given that as a disclaimer, here's my .02$ contribution:

>3)  can an architecture which is not load/store qualify as RISC?
No.

>5)  is it RISC if it doesn't have delayed load?  delayed branch?
Yes.

>6)  does an instruction set with variable-length instructions qualify as
>	RISC?
No.

The remaining 4 points have arbitrary answers and seem
peripheral to the general design philosophy. 

However, the more state that needs to be kept for complex
instructions that required implied sequences will complicate
error recovery in the machine. This provides sufficient 
encouragement to ISA designers to eliminate complexity 
until system-wide performance is shown to suffer. Apply 
Occam's razor, your milage may vary.

Richard Trauben
Sun MicroSystems
Mt. View, California