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From: marc@oahu.cs.ucla.edu (Marc Tremblay)
Newsgroups: comp.arch
Subject: Multi-Ported Register File
Message-ID: <34153@shemp.CS.UCLA.EDU>
Date: 12 Apr 90 22:43:59 GMT
Sender: news@CS.UCLA.EDU
Reply-To: marc@oahu.cs.ucla.edu (Marc Tremblay)
Organization: UCLA Computer Science Department
Lines: 25


	Recent chip designs have taken advantage of wide instruction
paths to fetch, decode and issue more than one instruction per cycle.
These chips need a multi-ported register file to sustain
the bandwith necessary to provide several operands per cycle.
For example the Intel 80960CA is advertised as having a 6-port
register file (though some ports are probably time-multiplexed).

	I have previously designed a standard dual-port static register
file (two simultaneous reads, one write per cycle) and I was wondering
if the same kind of circuits normally used for a simple register file
is used for a multi-ported register file.
For example I was wondering if a design with cross coupled inverters driving
the data lines through access transistors is still a valid choice.
Another interesting aspect is the design of the few decoders required
to access the ports. Some of these can be time-multiplexed but
that still requires a lot of area for the remaining decoders.

	There are other important factors such as the forwarding unit
and the load interlock circuitry associated with a multi-ported
register file. Briefly, there is a lot to discuss and besides
it is not a RISC vs. CISC topic!

					Marc Tremblay
					marc@CS.UCLA.EDU