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From: bron@bronze.wpd.sgi.com (Bron Campbell Nelson)
Newsgroups: comp.arch
Subject: Re: Multi-Ported Register File
Summary: How many ports?
Message-ID: <56847@sgi.sgi.com>
Date: 14 Apr 90 22:45:39 GMT
References: <34153@shemp.CS.UCLA.EDU> <11426@june.cs.washington.edu>
Sender: bron@bronze.wpd.sgi.com
Organization: Silicon Graphics, Inc., Mountain View, CA
Lines: 16

In article <11426@june.cs.washington.edu>, upton@badger.cs.washington.edu (Michael Upton) writes:
> 
> In reguards to the design of multiported register files:

One thing I've wondered .. how much extra chip area does it take to
build a multi-port register file?  The late lamented MultiFlow VLIW
machine, and the new crop of "super-scalar" chips that issue several
instructions per clock must be able to read and write large numbers of
registers simultaneously (something on the order or 10 reads and 5 writes
per clock).  How much extra hardware is needed to do this?  How many more
levels of logic are required over the "2 read 1 write" case?

--
Bron Campbell Nelson
bron@sgi.com  or possibly  ..!ames!sgi!bron
These statements are my own, not those of Silicon Graphics.