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From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.arch
Subject: Re: Multi-Ported Register File
Message-ID: <37918@mips.mips.COM>
Date: 15 Apr 90 02:18:40 GMT
References: <34153@shemp.CS.UCLA.EDU> <11426@june.cs.washington.edu> <56847@sgi.sgi.com>
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Reply-To: mark@mips.COM (Mark G. Johnson)
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In article <56847@sgi.sgi.com> bron@bronze.wpd.sgi.com (Bron Campbell Nelson) writes:
    >> In reguards to the design of multiported register files:
    >
    >One thing I've wondered .. how much extra chip area does it take to
    >build a multi-port register file?  The late lamented MultiFlow VLIW
    >machine, and the new crop of "super-scalar" chips that issue several
    >instructions per clock must be able to read and write large numbers of
    >registers simultaneously (something on the order or 10 reads and 5
    >writes per clock).  How much extra hardware is needed to do this?

Consider, for a moment, the _hypothesis_ that superscalar CPUs require
many-many-ported register files, *and* physical implementation of
these additionally-ported files requires more hardware than the (2R,1W)
register files of olden (nonsuperscalar) days.  Just a hypothesis; it
may or may not be true in real life.  Wouldn't it be unpleasant if
you had to add this extra hardware to a Large register file, like
for example, one that had 7 or 8 windows of 16 regs per window?
A penalty multiplied by a penalty, it might seem.


:-) :-) of course, gate arrays ARE getting denser all the time ... :-) :-)
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
	(408) 991-0208    mark@mips.com  {or ...!decwrl!mips!mark}