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From: chen-dahe@CS.Yale.EDU (Dahe Chen)
Newsgroups: comp.lsi.cad,comp.lsi
Subject: Routing of power/ground nets.
Keywords: routing, power/ground net, minimization.
Message-ID: <22624@cs.yale.edu>
Date: 14 Apr 90 05:06:26 GMT
Sender: news@cs.yale.edu
Reply-To: chen-dahe@CS.Yale.EDU (Dahe Chen)
Followup-To: comp.lsi.cad
Organization: Yale University Computer Science Dept, New Haven CT  06520-2158
Lines: 23

Hello, everyone,

As far as I know, the routing of power/ground nets is confined on
a single metal layer. I am wondering if this is still true nowadays.
If so, can someone enlighten me why this is the case though multiple
metal layers are available? The only reason I can think of is to
avoid vias. Are vias really so bad for power/ground nets?

Another thing is the minimization of the area for power/ground nets.
It seems to me that people forgot that the goal is to minimize the
TOTAL area of a chip when they were talking about the minimization of
the area for power/ground nets. In another word, minimizing the area
for power/ground nets does not necessarily lead to the minimization
of the chip area.

Any comments are welcome.


----------------------
Dahe Chen
internet:   dchen@twolf.ce.yale.edu
	    chen-dahe@cs.yale.edu
bitnet:	    dchen@yalevms