Path: utzoo!utgpu!news-server.csri.toronto.edu!clyde.concordia.ca!uunet!tut.cis.ohio-state.edu!pacific.mps.ohio-state.edu!zaphod.mps.ohio-state.edu!van-bc!ubc-cs!uw-beaver!Teknowledge.COM!unix!hplabs!hpfcso!hpldola!hp-lsd!dave
From: dave@hp-lsd.COS.HP.COM (David C. Mueller)
Newsgroups: comp.realtime
Subject: Re: Predicting Execution Times for Processors with caches
Message-ID: <15630006@hp-lsd.COS.HP.COM>
Date: 12 Apr 90 15:56:39 GMT
References: <765@telesoft.com>
Organization: HP Logic Systems Division - ColoSpgs, CO
Lines: 13

>
>Depending on the design of the cache in question, assuming that a random
>state cache is the same as an empty cache is not a safe assumption, nor
>will it result in identical execution times.
>
>One possibility which comes to mind is that a non-writethru cache which
>has modified (dirty) data from some other (preempted) thread in it has to
>write that modified data back to memory as new data is brought in. A
>flushed cache would thus run faster since it has no dirty data to write
>back to memory.

	Good example.  It is my understanding however, that the
68020/030 does not support non-writethru data caches.