Path: utzoo!attcan!uunet!snorkelwacker!think!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!ames!amdcad!pepsi!phil
From: phil@pepsi.amd.com (Phil Ngai)
Newsgroups: comp.sys.ibm.pc
Subject: Re: A wierd question on PC performance.
Keywords: bus limits, caching, memory
Message-ID: <29762@amdcad.AMD.COM>
Date: 6 Apr 90 19:20:18 GMT
References: <1758@watserv1.waterloo.edu> <10849@portia.Stanford.EDU>
Sender: news@amdcad.AMD.COM
Reply-To: phil@pepsi.AMD.COM (Phil Ngai)
Distribution: comp
Organization: Advanced Micro Devices, Inc. Sunnyvale CA
Lines: 9

I could be wrong, but I think something missing in this conversation
between the poster and David is that a 64K cache does not cache
64K bytes of contigious memory. A cache is usually divided into
blocks of maybe 32 bytes and each block can be mapped anywhere
as needed.

--
Phil Ngai, phil@amd.com		{uunet,decwrl,ucbvax}!amdcad!phil
Spring is here!