Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!brutus.cs.uiuc.edu!apple!voder!pyramid!cbmvax!daveh From: daveh@cbmvax.commodore.com (Dave Haynie) Newsgroups: comp.sys.mac.hardware Subject: Re: MacSprint II vs. PMMU upgrade Message-ID: <10775@cbmvax.commodore.com> Date: 11 Apr 90 04:29:58 GMT References: <9325@sdcc6.ucsd.edu> <77800010@m.cs.uiuc.edu> <1460@bridge2.ESD.3Com.COM> Reply-To: daveh@cbmvax (Dave Haynie) Organization: Commodore, West Chester, PA Lines: 31 In article <1460@bridge2.ESD.3Com.COM> ngg@bridge2.ESD.3Com.COM (Norman Goodger) writes: >In article <77800010@m.cs.uiuc.edu> gillies@m.cs.uiuc.edu writes: >>(1) The PMMU will actually *slow down* your computer. I believe the >> motorola chip has 1 more wait state than the apple chip. > As far as I know, this is incorrect. Installing the PMMU > removes the wait state, and does "not" slow down your Mac II. I don't know what the Apple MMU-replacement chip actually does. But the 68851 PMMU *ALWAYS* adds at least one wait state to a normal 68020 cycle. Nothing you can do about it. The worst part of it is that the MMU's bus timing is sloppy as compared with the 68020 timing, even though they use the same bus interface. So you can actually add two wait states with the PMMU, though not necessarily -- that's very dependent on the design of the system. The Mac II's memory system isn't fast enough for a 3 clock 68020 cycle anyway. The question is whether 4 or 5 clock memory cycles are actually used. If it's running 5 clocks, there's a real good chance Apple could have done 4 with a 68020 or 68030 instead of the 68020+68851, if they had been clever. They had the chance in the Mac IIx, but I don't think they started getting clever until the Mac IIci. >Norm Goodger SysOp - MacInfo BBS @415-795-8862 -- Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Too much of everything is just enough