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From: logajan@ns.network.com (John Logajan)
Newsgroups: sci.electronics
Subject: Re: A 74F74?
Message-ID: <1990Apr8.061809.6501@ns.network.com>
Date: 8 Apr 90 06:18:09 GMT
References: <9561@sdcc6.ucsd.edu> <37746@mips.mips.COM> <1990Apr8.000826.16803@utzoo.uucp>
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henry@utzoo.uucp (Henry Spencer) writes:
>Actually, 74F is a Really Nice family.  Not only is it fast as blazes, it
>tends to eat a lot less power than 74S, and is better-behaved in all kinds
>of little ways.

I use 74F parts here at Network almost exclusively for my logic needs.  It
has the good gate propagations speeds (6ns worst for simple gates and 10ns
clock to Q delays on most registers.)  You can run into problems at these
speeds due to the need to account for speed of light delays in connecting
foils between IC's.  We don't use a lot of line termination, but I have
seen enough cases where it is sometimes advisable (hint, if the line is
long and/or the frequency/pulse is high/fast.)  You get signal reflection
in all unterminated lines, but at high speeds there may not be enough time
in your design to let it settle out.  And our designs are always pushing
the edge.

The new kid on the block is 74FCT and 74FC (F.A.C.T.) which are almost as
fast as 74F, but are really CMOS based familes (with 74FCT being voltage
level compatible with TTL.)  Naturally their power requirements are less
still than 74F.

>Not least of its virtues is that since it came from Fairchild, it has
>truly exemplary datasheets, which pin down both minimum and maximum times
>and do so over the full temperature and voltage range, unlike most TTL
>datasheets.

Knowing minimum times becomes essential at high speeds due to the fact that
your clock skew between parts, say one register feeding another, may start
to exceed your minimum propogation time -- thus you could "short-path".
I.E. your data could arrive at the inputs to the next stage before that
stage saw it's clock.  When the clock does arrive, it will clock thru the
new data, rather than the "previous" data.  In effect, you will have your
data getting through two stages of registers in ONE clock time.  Very
bad if you aren't expecting it!!!

Of course, you can design around this problem with careful matching of
clock foil lengths, and other clock distribution techniques, but even then,
your clock fanout parts may have part-to-part speed variations that begin
to exceed your minimum times.  (I hate parts that spec ZERO as minimum
times.  You know they are lying because they don't want to have to control
the minimum time.  Fortunately, most such parts are inbetween parts with
spec'd minimums.  But processors always give me grief.  I know that I am
actually designing things that violate the theoretical spec/skew problem,
but I know that there are no such beasties as ZERO delay parts -- YET.)

-- 
- John Logajan @ Network Systems; 7600 Boone Ave; Brooklyn Park, MN 55428
- logajan@ns.network.com, john@logajan.mn.org, 612-424-4888, Fax 424-2853