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From: mshute@cs.man.ac.uk (Malcolm Shute)
Newsgroups: comp.arch
Subject: Re: RISC definition
Message-ID: <1252@m1.cs.man.ac.uk>
Date: 2 May 90 16:23:22 GMT
References: <2756@sunquest.UUCP> <151@exodus.Eng.Sun.COM> <1192@m1.cs.man.ac.uk> <1990Apr27.161912.15649@robohack.UUCP>
Sender: news@cs.man.ac.uk
Reply-To: mshute@cs.man.ac.uk (Malcolm Shute)
Organization: Department of Computer Science, University of Manchester UK
Lines: 59

>In article <1192@m1.cs.man.ac.uk> I wrote:
>>[A suggestion that we should define a metric so that RISC vs CISC was
>>no longer a black/white issue, but a sliding scale, say from 0.0 to 1.0]

In article <1990Apr27.161912.15649@robohack.UUCP> sanwalk@robohack.UUCP (A. Roy Sanwalka) writes:
>[Some sensible objections on grounds of implementation vs architecture]
>[A good reductio ad absurdum indication (it didn't have the power of a
>proof) that defining ultimate RISC and CISC instruction sets won't give
>us a sensible metric]

He also writes:
>Sure thing Malcolm, whatever you say...
I take your point... and the text which follows won't be any closer
to sanity I'm afraid (I'm relying on everyone's ability to hit the 'n' key
when they wish).  HOWEVER... I would like to stretch the idea just a bit
further, and ask the net if they can see any glimmer of hope in the
following idea:

Since measuring the instruction set complexity directly has been shown
to be unworkable (the reductio ad absurdum above), suppose we were to
adopt an indirect method.  Suppose we were to define a metric which is
the quotient of:

	(chip area of random logic) / (total chip area)

we would have to *define* what is meant by 'area of random logic',
for instance:

	(total chip area) - (area of regular logic)

and then *define* what *can* be included in 'regular logic', for example:

	1) area of chip that acts as cache memory
	2) any area that acts as a register bank
	3) any area that contains a regular bus (at least a byte wide)

We would have a metric which RISCs would tend to score low on, and CISCs
would tend to score high on.

What would be the point of it all?

The next time we have a "This is a RISC.  No, it's a CISC" discussion,
the above coefficient might lend a *little* weight to the argument.

Notice that I am not claiming that it will *define* the difference
between RISC and CISC, just act as metric which might shed some extra
light on the question.

Notice also, that I recognise that this metric is most definitely
measuring implementation rather than architecture, which is a pity,
but there we are.

As I say, I would be interested in any constructive response to such
a suggestion.  As I admitted in my original posting, it's all a bit
irrelevent in the end (so I would appreciate that flames and non constructive
responses be converted into the silent hitting of the 'n' key).
--

Malcolm SHUTE.         (The AM Mollusc:   v_@_ )        Disclaimer: all