Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!bpa!cbmvax!bryce
From: bryce@cbmvax.commodore.com (Bryce Nesbitt)
Newsgroups: comp.arch
Subject: WANTED: Research papers on memory/DRAM access tweaks
Message-ID: <11275@cbmvax.commodore.com>
Date: 3 May 90 08:08:08 GMT
Reply-To: bryce@commodore.COM (Bryce Nesbitt)
Organization: Commodore Technology, West Chester, PA
Lines: 34




I'm looking for hard data on the performance tradeoffs of various tweaks
to get higher performance from memory subsystems.  Techniques such as
interleaving banks, fast page mode rams, static column, prefetching, etc.

Typically a penalty is associated with doing the "wrong" thing, while "correct"
memory access are faster.  There is a tradeoff point, and I wish to explore
the available data.



Here is a real-life example: a Motorola 68030 system.  With normal DRAM it
takes 4 cycles for a memory access.  With static column DRAM (SCRAM), page
misses are 5 cycles, hits with the same column address are 3 cycles.  On top
of SCRAM, 68030 burst cycles can be added at 2 cycles each.

		normal DRAM		  4

		SCRAM (page miss)         5
		SCRAM (page hit)          3
		SCRAM burst		  X + 2 + 2 + 2

Would you enable SCRAM mode?  Would you enable burst mode for instructions?
For data?  I have an answer to the above questions, but would like to compare
notes with published data.  What papers are available?

-- 
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{o O} .     Bryce Nesbitt, Commodore-Amiga, Inc.
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