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From: lamaster@pioneer.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: RISC definition
Message-ID: <48577@ames.arc.nasa.gov>
Date: 3 May 90 17:18:22 GMT
References: <2756@sunquest.UUCP> <151@exodus.Eng.Sun.COM> <1192@m1.cs.man.ac.uk> <1990Apr27.161912.15649@robohack.UUCP> <1252@m1.cs.man.ac.uk>
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Reply-To: lamaster@pioneer.arc.nasa.gov (Hugh LaMaster)
Organization: NASA Ames Research Center, Mtn Vw CA 94035
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In article <1252@m1.cs.man.ac.uk> mshute@cs.man.ac.uk (Malcolm Shute) writes:
>>In article <1192@m1.cs.man.ac.uk> I wrote:
>>>[A suggestion that we should define a metric so that RISC vs CISC was
>>>no longer a black/white issue, but a sliding scale, say from 0.0 to 1.0]

>The next time we have a "This is a RISC.  No, it's a CISC" discussion,
>the above coefficient might lend a *little* weight to the argument.


The problem with this debate is that the premise is incorrect.  The unstated
premise is that RISC vs CISC is an important performance metric worth
measuring.  But, what definition of "RISC" gives the distinction a
difference?  Is there an architectural definition of RISC?

Better to ask: Why have so many implementations of VAX, 68k, etc, been "slow"
(such that comparable silicon implementations of competing architectures,
such as MIPS, have been faster)?

The difference is simply that the "slow" machines all have operand specifiers
which need to be decoded.  Therefore, a meaningful definition of RISC vs
CISC is just that: simple operand specifiers vs decoded operand specifiers.
All you need to do is come up with some sort of phrasing of that fact so
that the acronyms are RISC and CISC :-)



On a related tangent, for at least five years I have been hearing rumors of
"clever" operand specifier decode schemes which will obliterate this problem
and make VAX, 68K, etc. look just as fast as "RISC"s.  For some reason, these
schemes were always just around the corner, but, as soon as they hit, would
show that "RISC" was just a flash in the pan.  Again, with new implementations
of "RISC"s coming out, more hints have been dropped in various trade rags, etc.

Does anyone know for sure whether or not such schemes were used in the VAX 9000,
68040, or other places, and, if so, how much performance has been regained,
and, at what cost in gates/transistors/chip real estate/etc.?
For example, if it took a large translation buffer of some sort to do it, 
how large? 
Could three operands be decoded in parallel?  
How are deferred address modes supported, and do they cause serialization?

  Hugh LaMaster, M/S 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)604-6117