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From: scott@labtam.oz (Scott Colwell)
Newsgroups: comp.arch
Subject: Re: WANTED: Research papers on memory/DRAM access tweaks
Message-ID: <4392@labtam.oz>
Date: 4 May 90 01:13:31 GMT
References: <11275@cbmvax.commodore.com>
Organization: Labtam Limited., Melbourne, Australia
Lines: 29

From article <11275@cbmvax.commodore.com>, by bryce@cbmvax.commodore.com (Bryce Nesbitt):
> I'm looking for hard data on the performance tradeoffs of various tweaks
> to get higher performance from memory subsystems.  Techniques such as
> interleaving banks, fast page mode rams, static column, prefetching, etc.
> 
> Typically a penalty is associated with doing the "wrong" thing, while "correct"
> memory access are faster.  There is a tradeoff point, and I wish to explore
> the available data.

James Goodman and Men-chow Chiang presented a paper at the '84 Symposium
on Computer Architecture titled "The Use of Static Column RAM as a
Memory Hierarchy" which presented some trace driven simulations for
a VAX and a PDP-11. It covers using page mode on multiple banks as a means
of 'cacheing' data.  While the simulations are for rather dated cpu
architectures, the information does provide some idea on what hit rates
need to be achieved to break-even for various numbers banks in page/static
column mode.

The data is predominantly for large numbers of banks which tends to
be unrealistic with 1M and 4M drams however.

(I used this paper as input to the design of a memory controller for
a 20MHz 80386 and achieved very satisfactory results.)


-- 
Scott Colwell
Labtam Information Systems P/L	net:	scott@labtam.oz.au
Melbourne, Australia 		phone:	+61-3-587-1444