Path: utzoo!utgpu!cunews!bcars8!bnrgate!bigsur!bnr-rsc!bcarh185!schow From: schow@bcarh185.bnr.ca (Stanley T.H. Chow) Newsgroups: comp.arch Subject: Re: ECC Message-ID: <2829@bnr-rsc.UUCP> Date: 7 May 90 21:10:41 GMT References: Sender: news@bnr-rsc.UUCP Reply-To: bcarh185!schow@bnr-rsc.UUCP (Stanley T.H. Chow) Organization: BNR Ottawa, Canada Lines: 14 Summary: Followup-To: Keywords: In article aglew@dwarfs.csg.uiuc.edu (Andy Glew) writes: > Q: does anyone know of "sometimes" ECC systems? In our central office telephone switches, we have ECC that is sometimes switched off. Specifically, we switch off ECC when we are running in "Lock-step Sync" on matched processor pair with every cycle matched for error. (The ECC is always writen into memory, just the check is suppressed.) Stanley Chow BitNet: schow@BNR.CA BNR UUCP: ..!psuvax1!BNR.CA.bitnet!schow (613) 763-2831 ..!utgpu!bnr-vpa!bnr-rsc!schow%bcarh185 Me? Represent other people? Don't make them laugh so hard.