Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!cbmvax!grr From: grr@cbmvax.commodore.com (George Robbins) Newsgroups: comp.sys.amiga.hardware Subject: Re: Cheap CPU cache (was Re: A500/14 MHz 68k?) Message-ID: <11458@cbmvax.commodore.com> Date: 9 May 90 09:16:22 GMT References: <8903@chaph.usc.edu> <10630@cbmvax.commodore.com> <3596@pikes.Colorado.EDU> <3673@minyos.xx.rmit.oz> <943@mpirbn.UUCP> <948@mpirbn.UUCP> Reply-To: grr@cbmvax (George Robbins) Organization: Commodore, West Chester, PA Lines: 20 In article <948@mpirbn.UUCP> p554mve@mpirbn.UUCP (Michael van Elst) writes: > In article brent@asparagine.phri.nyu.edu (Brent Hobbs) writes: > >In article <943@mpirbn.UUCP> p554mve@mpirbn.UUCP (Michael van Elst) writes: > >> A second approach does give about 70-80% speedup on average programs and > >> will affect kickstart operations as well. This is a cache for the CPU. > > The design is published in the german magazine 'ST Computer' from > 'Markt&Technik'. For curiousity's sake, do you know what issue this was in? It's a little hard to search though German magazines from here... Personally, I'd have to wonder about the wisdom of a cacheing scheme - I'd expect the cost/complexity to be about the same as implementing a fast DRAM system... -- George Robbins - now working for, uucp: {uunet|pyramid|rutgers}!cbmvax!grr but no way officially representing: domain: grr@cbmvax.commodore.com Commodore, Engineering Department phone: 215-431-9349 (only by moonlite)