Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!elroy.jpl.nasa.gov!jarthur!nntp-server.caltech.edu!tybalt.caltech.edu!toddpw From: toddpw@tybalt.caltech.edu (Todd P. Whitesel) Newsgroups: comp.sys.apple2 Subject: Re: Memory chips, was: Re: BITNET mail follows Message-ID: <1990May3.215305.11551@laguna.ccsf.caltech.edu> Date: 3 May 90 21:53:05 GMT References: <9005022007.AA01369@apple.com> Sender: news@laguna.ccsf.caltech.edu Organization: California Institute of Technology Lines: 41 cs4w+@andrew.cmu.edu (Charles William Swiger) writes: >The speed of chip refers the time in nanoseconds that the chip requires >to perform a memory access. You really don't need chips that run faster >than the CPU (and/or the DMA controller) can possibly access them. From >what I remember about the timing cycle for memory access in Apple //'s, >you have 2/5's of the total time of one (CPU) clock cycle to do the >memory access. Sorry to nitpick, but that's not true. You have a lot more time than that, more like 4/5. The Apple // bus originally ran slow enough that all memory could be enabled using much simpler logic, but that only left about 2/5 of the clock cycle (which in a 1 mhz system is still 400 ns -- plenty of time). > Working that out shows that you need 143 ns chips to run >at 2.8 MHz. Since the chips aren't rated to run quite that fast, >ocasionally they'll be forced to cause a wait cycle, which gives them >time do finish the access at the cost of taking an extra (CPU) clock >cycle. Running the 150 ns chips at 2.8 mhz is not the cause of the wait cycle. DRAMs use a much smaller memory cell design (essentially a capacitor with a switch) which makes them hold more memory but requires that they be "refreshed" every so often in order to ensure that no data is lost do to capacitor charge leaking (don't laugh, I've actually seen it happen in a project I built!). It is pauses for refresh that cause the wait cycles. When running out of ROM or at 1 mhz the DRAM is refreshed automatically so no speed penalty occurs. The REAL reason why we should be using 120 ns or better is that you can run 120 ns DRAM at 3.58 Mhz (150's can't, for a reason similar to your argument above) and 3.58 Mhz is much nicer to work with because it is much more simply related to the rest of the machine. You can also "page mode" the DRAMs at 7.1 Mhz (double 3.58 mhz), and for cache and DMA (lots of sequential memory accesses) this gets a cheap doubling in speed. Page Mode is not hard to do: the VGC chip in the GS already uses it. There are so many simple things that could be done to the GS to really make it sing. Todd Whitesel toddpw @ tybalt.caltech.edu