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From: toddpw@tybalt.caltech.edu (Todd P. Whitesel)
Newsgroups: comp.sys.apple2
Subject: Re: Memory chips, was:  Re: BITNET mail follows
Message-ID: <1990May4.094936.27193@laguna.ccsf.caltech.edu>
Date: 4 May 90 09:49:36 GMT
References: <9005022007.AA01369@apple.com> <MaDwIcS00W05I5I1l_@andrew.cmu.edu> <12630@wpi.wpi.edu>
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dseah@wpi.wpi.edu (David I Seah) writes:

>Apple seems to enjoy putting higher-rated parts into their hardware
>for improved reliability (like the greater-than-1Mhz 6502 in the Apple IIc).  

Not in this case. The 2 mhz 65C02 in the //e and //c is necessary, because
the custom chips (IOU/MMU) are so godawful slow that a 1 mhz 65c02 doesn't
give them enough time to decode the address.

Todd Whitesel
toddpw @ tybalt.caltech.edu