Path: utzoo!utgpu!news-server.csri.toronto.edu!clyde.concordia.ca!uunet!samsung!xylogics!world!madd
From: madd@world.std.com (jim frost)
Newsgroups: comp.sys.apple2
Subject: Re: Apple IIGS Rules! (vs IBM and Mac)
Message-ID: <1990May8.020332.26836@world.std.com>
Date: 8 May 90 02:03:32 GMT
References: <900505.18161082.042392@UWEC.CP6>
Organization: Saber Software
Lines: 47

S707503@UWEC.BITNET (MARK RINECK) writes:
>Of course MIPS is a better test for speed, but still, there is NO
>way a 2.8 MHZ machine is going to be faster than an 8 Mhz consistently.
>(there are always special exceptions...etc.)

Most CISC chips (such as the 8088) take two to six cycles per
instruction.  Most RISC chips take one to two and newer RISC chips are
superscalar -- better than one instruction per cycle.

A superscalar RISC chip, running at .8 cycles/instruction average,
needs only to run at less a third of the clock speed of a CISC chip to
achieve the same MIPS rating.

"Ah," you say, "but the CISC is getting more done per instruction."

True.  Common instructions, such as "add", can take three or four
instructions in a RISC architecture -- load registers, add registers,
save registers.  You see your advantage dwindling.  But then you do
optimization.

In a RISC architecture the software has a lot better control of how
data flows in and out of the CPU.  It's pretty easy to do dataflow
analysis to determine which things to keep in registers and which not,
thus cutting out a lot of those loads and stores and boosting
performance -- in a CISC architecture all that streamlining is
hardcoded into the CPU and if it doesn't quite match what you want to
do, it's too bad.

What you tend to see is RISC applications performing at about the same
speed as CISC applications but at only about 70% of the clock speed
(in other words, they run quite a bit faster at the same clock speed).
A lot of this advantage is getting eliminated by CISC manufacturers
making use of RISC techniques inside of their processors, boosting
performance.  And the RISC designers are going off and using
parallelism to push more instructions through in the same time --
sometimes four or more instructions in a single cycle.

What does this have to do with the topic at hand?  It *is* possible
that a processor running at less than half the clock speed of another
can outperform the other, even comparing CISC to CISC performance.
For a real-life comparison, check out the MC68030 vs the 040.
Although they implement the same instruction set the 040 runs
remarkably faster even at the same clock speed.

jim frost
saber software
jimf@saber.com