Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!microsoft!brianw
From: brianw@microsoft.UUCP (Brian WILLOUGHBY)
Newsgroups: comp.sys.apple2
Subject: Re: TransWarp III
Message-ID: <54522@microsoft.UUCP>
Date: 8 May 90 19:27:54 GMT
References: <11640.infoapple.net@pro-generic> <54323@microsoft.UUCP> <1990Apr30.093518.4994@laguna.ccsf.caltech.edu>
Reply-To: brianw@microsoft.UUCP (Brian WILLOUGHBY)
Organization: Microsoft Corp., Redmond WA
Lines: 138

In article <1990Apr30.093518.4994@laguna.ccsf.caltech.edu> toddpw@tybalt.caltech.edu (Todd P. Whitesel) writes:
>brianw@microsoft.UUCP (Brian WILLOUGHBY) writes:
>
>>I found it hard to believe (and still do) that some college kid has done a
>>better job all by himself than what the Western Design Center can do with
>>a team of engineers. [snip]
>
>WDC does not have "a team of engineers" -- they have Bill Mensch and his
>wife and daughter. The original 65816 mask was laid out BY HAND five
>years ago and they have NEVER tried using the state of the art gate array
>approach that Tony Fadell had the connections to gain access to.

So, you believe everything you read on the net?  Just because of the
"net legend" of the Mensch family, you have extrapolated that there are
no other WDC employess?  Someone at WDC did extensive research into the
interaction between the 65C8xx and the Apple Disk ][ card - has anyone
even powered up an Apple ][ with the ASIC chip in it?  Before I get all
happy about my future computing possibilities, I'd like to hear a little
more about what is behind ASIC.  Did you know that W.D.Mensch worked
for the company that originally designed the 6502?  I think that
qualifies him to do design work in his kitchen after a decade of
experience.  I hope you realize that WDC has MANY more customers than
Apple Co.  They happen to be very popular in the medical industry and
with embedded controllers.  WDC works with more than the Apple ][, but
the ASIC chip hasn't even done that yet!

>A couple years ago when I got my hands on the 65816 data sheet I took one
>look at the cycle-by-cycle bus state listing (all of two pages) and said
>"you know, this CPU is so damn simple it would make a great state machine"
>but I wasn't about to try to build one out of PALs and TTL...
>
>And a year and a half later I find out that somebody else at another college
>had the money and the connections to make a 65816 state machine.
>
>I am very disappointed in WDC that they did not think of this first.

Todd, I'm quite impressed with your knowledge of electronics, and I
enjoy hearing your ideas.  But what I don't enjoy is your ragging on
a company when you have no idea what they did.  I'll forgive you,
though, since this is obviously a religious issue :-)

How do you know that WDC *didn't* think of gate arrays?  I've learned
that gate arrays are great for quick, space-efficient design of logic
circuits - but the tradeoff is slower operation.  Hard-coded logic
takes longer to design, and requires custom fabrication, but the
resulting chip is generally faster.  Gate arrays are quicker and
cheaper to fabricate, bacause they are all the same.  There is no
difference between the ASIC 65C816 and some other chip - at least not
until the array is programmed for the specified circuit paths.  I
would hardly say that gate array is the optimum design choice for a
processor.  I suppose that we will find out, but I will wait for the
testing stage before I go counting my eggs.

>>In addition, WDC rates their processor speed by about 15 different timing
>>relationships.  They rate data and address input and output timing as well
>>as the relationship between different clock and control signals.  If any
>>ONE of those timing specs does not work at a particular speed, then the
>>chip is rated at a lower speed.  WDC has chips that might run at 20 MHz
>>(that's a guess on my part) in a custom circuit that is designed to work
>>around the slower timing ratios.  The fact is that the overall CPU speed
>>is based on many factors, with the slowest measured timing being the limit.
>
>No argument here, just don't see how it applies. The ASIC chip is a data
>file which gets handed to a chip house and they use it to configure a
>gate array they have already designed and tested. Fadell didn't specify
>that the chip would run at 20 mhz, the chip house told him that his design
>on their gate array would be able to run at 20 mhz with the necessary timing
>ratios.

It applies because WDC is qualifying their speed claims, but there is
no reference for the ASIC chips.  What do they mean by 15 MHz?  How can
a system (or an accelerator card) be designed to use the ASIC chip
around such an unqualified rating?  I can be sure of what it means when
WDC says their chip runs at a certain speed.  Without all the timing
specs, I don't trust the ASIC speed rating.  I still haven't heard of
anyone plugging an ASIC chips into a modified TransWarp and actually
running Apple ][ software...

>WDC's chips might run at 20 mhz -- if you have -10 ns SRAM. WDC's chips
>are, bluntly put, sloppily designed compared to the ASIC gate array.

Do you really know anything about how the WDC chip was designed?  Do
you know anything about how the ASIC chip is designed?  How do you know
which is sloppy and which isn't?  You seem to be making many statements
based purely on conjecture.

The ASIC chip would require the same speed SRAM as the WDC chip if they
were running at the same speed.

>>A common misconception about integrated circuits is the assumption that
>>there are different production runs for each chip speed.  Actually, a chip
>>manufacturer attempts to make every chip at top speed, and then tests the
>>performance before marking them.
>
>Well, that's true for each spread of speeds. Motorola makes two seperate
>production runs for 8-20 mhz chips and for 33-50 mhz chips.
>You're otherwise correct.

True, there are different technologies being developed all the time.
Each successive fabrication technology is generally smaller and faster.
Motorola simply didn't shut down their old fabrication facilities
because they know that there is a market for the slower (cheaper) chips.

Here's an idea: perhaps WDC still produces 65C8xx's with medium speed
technology because the bulk of their customers (not Apple) only need a
certain amount of speed.  Without the capitol investment, and without
the promise that there will be a merket, I can see how WDC might not
be using the fastest fabrication technology until Apple is willing to
commit.  This is just a theorization on my part.

>>Don't forget that a 8 MHz 6502 is running like a 35 to 40 MHz 8088
>>(although I can't say what speed 80486 it can compete with).  Also, a
>>10 MHz 65C816 can keep up with a 20 MHz 68000 (but I wouldn't put it
>>up against a 68040).  This is not considering video or disk I/O.
>
>Barf! Cross CPU comparisons are generally meaningless. Comparing a IIGS at
>2.5 mhz under GS/OS w/ Appleworks GS to a 12 mhz 286 under windows 2 with
>Microsoft Works... _that_ means something.

Ok, I admit that such comparisons are not final, but I am just tired
of so many people assuming that the clock speed of different processors
are interchangeable.  The point that I was making was that instead of
thinking that a 1 MHz 6502 is roughly equivalent to a 1 MHz PC (which
is way off), think of it as a 5 MHz PC (which isn't precise, but is
much closer to realistic).  My gripe is that 20 MHz seems to be a
goal that everyone on the net wants the ASIC chips to reach, and I
think that this is based on 20 MHz PC performance.  I just want to get
that sort of comparison out of people's heads.  There is much more to
computer performance than a couple of numbers.

>Todd Whitesel
>toddpw @ tybalt.caltech.edu

Brian Willoughby
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