Path: utzoo!utgpu!news-server.csri.toronto.edu!clyde.concordia.ca!uunet!lll-winken!uwm.edu!ux1.cso.uiuc.edu!ux1.cso.uiuc.edu!aglew From: aglew@dwarfs.csg.uiuc.edu (Andy Glew) Newsgroups: comp.arch Subject: Re: unexpected CPU behavior [was 486 bugs -- it's in there!] Message-ID: Date: 28 May 90 02:55:56 GMT References: <1990May27.110726.17007@xavax.com> Sender: usenet@ux1.cso.uiuc.edu (News) Organization: University of Illinois, Computer Systems Group Lines: 19 In-Reply-To: alvitar@xavax.com's message of 27 May 90 11:07:26 GMT ..> Motorola's 68000 clr instruction quirk that read the addressed ..> location before clearing it - causing problems for active ..> memory mapped I/O locations. Comment: isn't this the sort of thing that comes with using the same instructions for I/O access as for memory? For memory access all we care about is the data returned or written - for I/O you have to specify exactly what bus transactions are used. It is perfectly reasonable to read before write for a clear instruction. Wasteful, but legitimate - it doesn't change the semantics from the point of view of what is actually written in memory. And it might be necessary, say, if you are doing a clear-byte operation, and your bus is word-wide, without partial writes. In that case, for memory mapped I/O you might expect the memory controller to handle the active memory locations specially - but isn't it possible that a special I/O instruction might make the distinction more easily? -- Andy Glew, aglew@uiuc.edu