Path: utzoo!attcan!uunet!samsung!usc!zaphod.mps.ohio-state.edu!rpi!sci.ccny.cuny.edu!phri!roy From: roy@phri.nyu.edu (Roy Smith) Newsgroups: comp.arch Subject: Re: unexpected CPU behavior [was 486 bugs -- it's in there!] Message-ID: <1990May28.124724.24879@phri.nyu.edu> Date: 28 May 90 12:47:24 GMT References: <1990May27.110726.17007@xavax.com> Sender: news@phri.nyu.edu (News System) Organization: Public Health Research Institute, New York City Lines: 18 aglew@dwarfs.csg.uiuc.edu (Andy Glew) writes: >> 68000 clr instruction quirk that read the addressed location before >> clearing it - causing problems for active memory mapped I/O locations. > Comment: isn't this the sort of thing that comes with using the same > instructions for I/O access as for memory? No, this is the sort of thing which comes from having write-only and read-only registers share the same bus address. Even on machines with very small I/O address spaces (4k on the pdp-11, I think it was) I never saw a configuration where you came close to filling the I/O address space. What harm could it really do to turn a 4-address controller with hairy twinned control and status registers into an 8-address one on which it was safe to do read-before-write cycles? -- Roy Smith, Public Health Research Institute 455 First Avenue, New York, NY 10016 roy@alanine.phri.nyu.edu -OR- {att,cmcl2,rutgers,hombre}!phri!roy "Arcane? Did you say arcane? It wouldn't be Unix if it wasn't arcane!"