Path: utzoo!attcan!uunet!mcsun!ukc!inmos!inmos.co.uk!davidb
From: davidb@inmos.co.uk (David Boreham)
Newsgroups: comp.arch
Subject: Unexpected CPU behavior and the CLR instruction
Message-ID: <7101@ganymede.inmos.co.uk>
Date: 29 May 90 11:08:56 GMT
Sender: news@inmos.co.uk
Reply-To: davidb@inmos.co.uk (David Boreham)
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I think that the reason why the 68K and '11 do a read/modify/write
on clear instructions is because they use the XOR ALU function to
perform the clear. The microcode simply performs a read, XOR with
its self, then write.

On machines with no clear, XOR is a good bet instead. This used to
be common in Z80 code and I'm sure in many other machines.

On the subject of ``errant memory cycles'' I think that most CPUs
perform these somewhere or other. For instance a common one with
transputers is that when a block move is timesliced (by the microcode),
the instruction is restarted possibly by performing a second read 
to a location perviously accessed. This means that using the block
move instruction on FIFO chips can get really interesting :)


David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb
Bristol,  England            |     (us): uunet!inmos.com!davidb
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