Newsgroups: comp.arch
Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!wuarchive!brutus.cs.uiuc.edu!ux1.cso.uiuc.edu!alix
From: alix@cerl.uiuc.edu (Chris Alix)
Subject: Re: unexpected CPU behavior [was 486 bugs -- it's in there!]
Message-ID: <1990May30.010715.14180@ux1.cso.uiuc.edu>
Keywords: 68000, clr
Sender: usenet@ux1.cso.uiuc.edu (News)
Organization: UIUC Computer-based Education Research Lab
References: <1990May27.110726.17007@xavax.com> <16744@haddock.ima.isc.com>
Date: Wed, 30 May 90 01:07:15 GMT
Lines: 33

In article <16744@haddock.ima.isc.com> (Jim McGrath) writes:
>> [Previous Posting about 68000 CLR instruction reading before writing]
>
>I remember it being quite an ugly problem because of a C compiler that
>used the CLR instead of MOVEQ.  The hardware group in my company had
>mapped a read-only and a write-only I/O port to the same address to
>save a bit of wire.  Trying to set the write only port to 0 caused a
>destructive read of the read-only port.  I only heard about this after
>the case because I was still programming in assembler and knew to
>avoid the CLR with I/O.

My (obvious) work-around (temp is unsigned char, ioaddr is an unsigned
char * to the device i/o register):

	temp = 0;
	*ioaddr = temp;

...which my compiler doesn't optimize into a CLR instruction.  the CLR
instruction behavior isn't a "bug" in the sense that Motorola describes it
in the manual, but I'd venture to guess that it wasn't an intentional
part of the original architecture specification.  Given the number of
device driver programmers who have been tripped up by an overzealous
optimizer in the case at hand, combined with the lack of situations in
which I have found the behavior useful, I consider the operation of
CLR a "mistake".

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Christopher Alix                               E-mail: alix@uiuc.edu
University of Illinois                  PLATO/NovaNET: alix / s / cerl
Computer-Based Education Research Lab           Phone: (217) 333-7439
103 S. Mathews  Urbana, IL  61820                 Fax: (217) 244-0793
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