Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!mips!servitude!rogerk From: rogerk@mips.COM (Roger B.A. Klorese) Newsgroups: comp.arch Subject: Re: Microprocessors and market forces Message-ID: <39165@mips.mips.COM> Date: 31 May 90 00:47:56 GMT References: <1990May14.141148.9884@xavax.com> <29972@cup.portal.com> <1990May18.170721.12758@utzoo.uucp> <2732@wyse.wyse.com> Sender: news@mips.COM Reply-To: rogerk@mips.COM (Roger B.A. Klorese) Organization: MIPS Computer Systems, Inc. Lines: 23 In article <2732@wyse.wyse.com> stevew@wyse.UUCP (Steve Wilson xttemp dept303) writes: >In article jim@cs.strath.ac.uk (Jim Reid) writes: >>Sequent went >>for the NS32032 (as opposed to an M68k) because it didn't have an >>on-chip cache which would have made a shared-memory multiprocessor box >>difficult to build. At that time (6-7 years ago), > >First question is how does an on-chip cache help with a shared-memory >multiprocessor box? It should make things more difficult due to >cache coherency issues. Also note that the 32032 didn't have >an on-chip cache either. Perhaps you mean the MMU(32032 didn't >have on-chip MMU, but did have a simi-working MMU chip.) You're right, and so's Jim; you just parsed his statement incorrectly. He said that Sequent went for the NS32032, as opposed to an M68K, because the NS part didn't have an on-chip cache, and on-chip caches would have made a shared-memory multiprocessor box like Sequent's difficult to build. -- ROGER B.A. KLORESE MIPS Computer Systems, Inc. phone: +1 408 720-2939 MS 4-02 950 DeGuigne Dr. Sunnyvale, CA 94086 voicemail: +1 408 524-7421 rogerk@mips.COM {ames,decwrl,pyramid}!mips!rogerk "I'm the NLA" "Maybe this world is another planet's hell." -- Aldous Huxley