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From: stevew@wyse.wyse.com (Steve Wilson xttemp dept303)
Newsgroups: comp.arch
Subject: Re: Microprocessors and market forces
Message-ID: <2732@wyse.wyse.com>
Date: 31 May 90 00:13:34 GMT
References: <1990May14.141148.9884@xavax.com> <29972@cup.portal.com> <AJI3HN4@xds13.ferranti.com> <1990May18.170721.12758@utzoo.uucp> <j5dps8023@tmsoft.uucp> <JIM.90May22114540@baird.cs.strath.ac.uk>
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In article <JIM.90May22114540@baird.cs.strath.ac.uk> jim@cs.strath.ac.uk (Jim Reid) writes:
>Sequent went
>for the NS32032 (as opposed to an M68k) because it didn't have an
>on-chip cache which would have made a shared-memory multiprocessor box
>difficult to build. At that time (6-7 years ago), 

First question is how does an on-chip cache help with a shared-memory
multiprocessor box?  It should make things more difficult due to 
cache coherency issues.  Also note that the 32032 didn't have 
an on-chip cache either.  Perhaps you mean the MMU(32032 didn't
have on-chip MMU, but did have a simi-working MMU chip.)

Steve Wilson