Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!uwm.edu!cs.utexas.edu!usc!apple!vsi1!wyse!stevew From: stevew@wyse.wyse.com (Steve Wilson xttemp dept303) Newsgroups: comp.arch Subject: Re: Microprocessors and market forces Message-ID: <2735@wyse.wyse.com> Date: 31 May 90 16:25:42 GMT References: <1990May14.141148.9884@xavax.com> <29972@cup.portal.com> <1990May18.170721.12758@utzoo.uucp> <2732@wyse.wyse.com> Sender: news@wyse.wyse.com Reply-To: stevew@wyse.UUCP (Steve Wilson xttemp dept303) Organization: Wyse Technology Lines: 27 In article <2732@wyse.wyse.com> stevew@wyse.UUCP (Steve Wilson xttemp dept303) writes: >In article jim@cs.strath.ac.uk (Jim Reid) writes: >>Sequent went >>for the NS32032 (as opposed to an M68k) because it didn't have an >>on-chip cache which would have made a shared-memory multiprocessor box >>difficult to build. At that time (6-7 years ago), > >First question is how does an on-chip cache help with a shared-memory >multiprocessor box? It should make things more difficult due to >cache coherency issues. Also note that the 32032 didn't have >an on-chip cache either. Perhaps you mean the MMU(32032 didn't >have on-chip MMU, but did have a simi-working MMU chip.) > >Steve Wilson As has been pointed out to me rather politely (as oppossed to the flame it probably deserved) I mis-read the original comment. Sorry about that folks.... Maybe the only useful item in the posting was that the MMU available from NSC at the time perhaps played a role in Sequent's decision. I know the MMU was an important factor for Tolerant System choosing the 32K. Steve Wilson