Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!usc!petunia!news
From: mdeale@sargas.acs.calpoly.edu (Myron Deale)
Newsgroups: comp.arch
Subject: Question on division methods
Message-ID: <26681c80.27e8@petunia.CalPoly.EDU>
Date: 2 Jun 90 20:07:28 GMT
Reply-To: mdeale@sargas.acs.calpoly.edu (Myron Deale)
Distribution: usa
Organization: ACS, Cal Poly, San Luis
Lines: 25




Hello, 
   I know this is a silly thing to try, but here's an article relating
to COMPuter ARCHitecture. If you're a compiler-driven type, press 'n'.

   I believe that given the ever increasing frequencies for micro-
processors, the division operation would do well by using a
shift-and-subtract method vs. using a multiplier based technique.
An extra shifter and subtractor would take up minimal chip area,
and division could procede *simultaneously* with multiplication.

   On the other hand, the i860 can produce a result every instruction
clock cycle. "Newton"s method could be accomplished in about 10 cycles;
although I hear the actual figure is more like 21-22 cycles (to account
for exponent processing?). But then the multiply unit is tied up for
the division operation, which could be a real performance hit on
certain applications.

   Reply via email please.


-Myron
// mdeale@cosmos.acs.calpoly.edu